Power and area-optimised Carry-Select Adder architecture for standard cell-based design
Author:
Affiliation:
1. SoC Design Lab, Department of Information and Communication Engineering, Chosun University, Gwangju, Republic of Korea
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2014.981870
Reference12 articles.
1. Optimized design of parallel carry-select adders
2. Carry-Select Adder
3. Carry-select adder using single ripple-carry adder
4. A new high performance circuit for statistical carry lookahead addition
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