Design of energy efficient domino logic circuit using lector technique
Author:
Affiliation:
1. Department of Electronics and Communication, Madan Mohan Malaviya University of Technology, Gorakhpur, U.P, India
2. Department of EEE, SCE, Sasaram, Bihar (Earlier with ECE Dept, MMMUT, Gorakhpur, (U.P.), India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2022.2145500
Reference28 articles.
1. Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style
2. High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits
3. A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology
4. A new low-power dynamic circuit for wide fan-in gates
5. Ultra-low power FinFET-based domino circuits
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