A novel differential XOR-based self-checking adder

Author:

Belgacem Hamdi,Chiraz Khedhiri,Rached Tourki

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Reference42 articles.

1. Fault and error models for VLSI

2. Anderson, DA. (1971), ‘Design of Self-checking Digital Networks using Coding Techniques’, Technical Report R-527, University of Illinois Coordinated Science Laboratory, Urbana, IL, September

3. Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes

4. Arithmetic Algorithms for Error-Coded Operands

5. Low Power Digital CMOS Design

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1. Fault tolerant system based on Iddq testing;International Journal of Electronics;2018-01-10

2. VLSI Implementation of Booth’s Multiplier Using Different Adders;Advances in Communication, Devices and Networking;2018

3. A Novel Energy-Efficient Hybrid Full Adder Circuit;Advances in Data and Information Sciences;2018

4. Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” [Dec 07 2696-2705];IEEE Transactions on Circuits and Systems I: Regular Papers;2014-07

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