Author:
Sharma Trapti,Kumre Laxmi
Reference20 articles.
1. Sabaghi M, Marjani S, Majdabadi A (2016) The design of ultra-low power adder cell in 90 and 180 nm CMOS technology. Circuits Syst 7(2):58–67
2. Wariya S, Nagaria R, Tiwari S (2012) Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design. VLSI Design 1–18
3. Jiang Y, Al-Sheraidah A, Wang Y, Sha E, Chung J-G (2004) A novel multiplexer-based low-power full adder. IEEE Trans Circuits Syst II 51(7):345–348
4. Wang D, Yang M, Cheng W, Guan X, Zhu Z, Yang Y (2009) Novel low power full adder cells in 180 nm CMOS technology. ICIEA 1:0
5. Zimmermann R, Fichtner W (1997) Low-power logic styles. IEEE J Solid State Circuit 32:1079–1090
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