Author:
Sethi Kabiraj,Panda Rutuparna
Subject
Electrical and Electronic Engineering
Cited by
15 articles.
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1. Energy Efficient Vedic Multiplier;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14
2. A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier;Analog Integrated Circuits and Signal Processing;2023-12-24
3. Analysis of Delay in 16 × 16 Signed Binary Multiplier;Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences;2023
4. Tableless Calculation of Circular Functions on Dyadic Rationals;Electronic Proceedings in Theoretical Computer Science;2022-06-30
5. Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA;2021 International Conference on Electrical, Computer and Energy Technologies (ICECET);2021-12-09