Phase-locked loop design with fast-digital-calibration charge pump
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2015.1036371
Reference17 articles.
1. A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser
2. A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
3. Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop
4. A fractional-N PLL with small ΔKvcowideband LC-VCO and current-matching CP for M-DTV systems
5. A State-Space Phase-Noise Model for Nonlinear MEMS Oscillators Employing Automatic Amplitude Control
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