A novel reversible carry-selected adder with low latency
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2015.1092595
Reference18 articles.
1. Elementary gates for quantum computation
2. Logical Reversibility of Computation
3. Quantum mechanical computers
4. A Novel Reversible BCD Adder For Nanotechnology Based Systems
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1. Front-End Design of 64-Bit Carry Look Ahead Adder;2023 International Conference on Sustainable Emerging Innovations in Engineering and Technology (ICSEIET);2023-09-14
2. A Brief Analysis of Fault-Tolerant Ripple Carry Adders with a Design for Reliable Approximate Adders;Proceedings of Second International Conference on Advances in Computer Engineering and Communication Systems;2022
3. Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders;Microelectronics Reliability;2021-12
4. Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits;Journal of Computational Electronics;2017-02-25
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