A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2013.805392
Reference22 articles.
1. GA Based Congestion Aware Topology Generation for Application Specific NoC
2. Power-aware multi-objective evolutionary optimisation for application mapping on network-on-chip platforms
3. Das, R., Eachempati, S., Mishra, A. K., Narayanan, V. & Das, C. R. (2009). Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. InHPCA 2009(pp. 175–186). February.
4. Designing fault-tolerant network-on-chip router architecture
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