A survey on fault-tolerant application mapping techniques for Network-on-Chip-Reference-Cited by-同舟云学术

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A survey on fault-tolerant application mapping techniques for Network-on-Chip

Published:2019-01 Issue: Volume:92 Page:39-52
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Kadri Nassima,Koudil Mouloud

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference137 articles.

1. Research challenges for on-chip interconnection networks;Owens;IEEE Micro.,2007

2. Networks on chips: a new soc paradigm;Benini;Computer (Long Beach Calif),2002

3. A network on chip architecture and design methodology;Kumar,2002

4. A survey on application mapping strategies for network-on-chip design;Sahu;J. Syst. Archit.,2013

5. Throughput optimization for lifetime budgeting in many-core systems;Wang,2017

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2. Model Comparative Analysis of Neighborhood Aggregation Levels in Graph Neural Networks for Metaschedulers;2024 IEEE International Conference on Industrial Technology (ICIT);2024-03-25

3. A survey on mapping and scheduling techniques for 3D Network-on-chip;Journal of Systems Architecture;2024-02

4. Towards Fault Tolerance and Resilience in the Sequential Codelet Model;Communications in Computer and Information Science;2024

5. Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey;Microprocessors and Microsystems;2023-11

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