Dispatching for order-driven FABs with backward pegging
Author:
Affiliation:
1. Department of Industrial Engineering, Ajou University , San 5, Woncheon-dong, Yeongtong-gu, Suwon 443-749, Korea
Funder
Ajou University
Publisher
Informa UK Limited
Subject
General Engineering,General Chemical Engineering,General Computer Science
Link
https://www.cogentoa.com/article/10.1080/23311916.2016.1226460.pdf
Reference20 articles.
1. Integrated lot sizing and dispatching in wafer fabrication
2. A WIP Balancing Procedure for Throughput Maximization in Semiconductor Fabrication
3. Long-term tool elimination planning for a wafer fab
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