A performance analysis of dispatch rules for semiconductor assembly & test operations
Author:
Affiliation:
1. Graduate Program in Operation Research & Industrial Engineering, University of Texas, Austin, TX, USA
2. Information, Risk and Operation Management Department, McCombs School of Business, The University of Texas, Austin, TX, USA
Publisher
Informa UK Limited
Subject
Modeling and Simulation,Software
Link
https://www.tandfonline.com/doi/pdf/10.1080/17477778.2018.1453255
Reference28 articles.
1. Scheduling algorithms for a semiconductor probing facility
2. Daily scheduling of multi-pass lots at assembly and test facilities
3. Integrating optimisation and simulation approaches for daily scheduling of assembly and test operations
4. Queueing Model Improves IBM's Semiconductor Capacity and Lead-Time Management
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1. A Generation and Repair Approach to Scheduling Semiconductor Packaging Facilities Using Case-Based Reasoning;IEEE Access;2023
2. Scalable Scheduling of Semiconductor Packaging Facilities Using Deep Reinforcement Learning;IEEE Transactions on Cybernetics;2021
3. A Reinforcement Learning Approach to Robust Scheduling of Semiconductor Manufacturing Facilities;IEEE Transactions on Automation Science and Engineering;2020
4. Simulation Study for Semiconductor Manufacturing System: Dispatching Policies for a Wafer Test Facility;Sustainability;2019-02-20
5. Learning to Dispatch Operations with Intentional Delay for Re-Entrant Multiple-Chip Product Assembly Lines;Sustainability;2018-11-09
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