Simulation Study for Semiconductor Manufacturing System: Dispatching Policies for a Wafer Test Facility

Abstract

The manufacture of semiconductor products requires many dedicated steps, and these steps can be grouped into several major phases. One of the major steps found at the end of the wafer fabrication process is the electrical die sorting (EDS) test operation. This paper focuses on dispatching policies in an EDS test facility to reduce unnecessary work for the system. This allows the semiconductor manufacturing facility to achieve better overall efficiency, thereby contributing to sustainable manufacturing by reducing material movements, the use of testing machines, energy consumption, and so on. In the facility, wafer lots are processed on a series of workstations (cells), and the facility holds identical parallel machines. The wafers are moved by an automatic material handling system from cell to cell as well as within cells. We propose several scheduling policies consisting of intercell and intracell material movements for efficient system operation. For this, four intercell scheduling policies and two intracell scheduling policies are introduced, and the effects of combinations are tested and evaluated through simulation experiments to obtain performance measures such as cycle time and work in process. The most efficient results among the combinations are presented as a proposed scheduling policy for a given EDS test facility.