Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications-Reference-Cited by-同舟云学术

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Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

Published:2020-12-09 Issue: Volume: Page:1-12
ISSN:0256-4602
Container-title:IETE Technical Review
language:en
Short-container-title:IETE Technical Review

Author:

Das Suman¹²,Chattopadhyay Avik²,Tewari Suchismita²

Affiliation:

1. Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim Manipal University, 737136 Sikkim, India

2. Institute of Radio Physics and Electronics, University of Calcutta, 92 Acharya Prafulla Chandra Road, 700009 Kolkata, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/02564602.2020.1852120

Reference35 articles.

1. Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model

2. Analytical Modeling and Performance Characterization of a Double Gate MOSFET with Dielectric Pockets Incorporating Work Function Engineered Binary Metal Alloy Gate Electrode for Subdued SCEs

3. Vertical Tunnel Field-Effect Transistor

4. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric

5. The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative analysis of performance and its stability against real-time non-ideal conditions between DG-TFET sensor and its MOS equivalent for a range of biomolecule detection: a design perspective;AEU - International Journal of Electronics and Communications;2024-04

2. Effect of Channel Epilayer Thickness on Low Power Analog Operation of Asymmetric U-Shaped pTFET;Springer Proceedings in Physics;2024

3. Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness;AEU - International Journal of Electronics and Communications;2023-08

4. Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study;IEEE Transactions on Electron Devices;2022-11

5. Thermal Effect of Analog/RF Performance, Linearity and Harmonic Distortion for L-Gate TFET;Silicon;2022-02-17

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