An Overview of Bipolar Gate Arrays and a Report of an IIL Gate Array Design and Development-Reference-Cited by-同舟云学术

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An Overview of Bipolar Gate Arrays and a Report of an IIL Gate Array Design and Development

Published:1990-09 Issue:5-6 Volume:7 Page:320-327
ISSN:0256-4602
Container-title:IETE Technical Review
language:en
Short-container-title:IETE Technical Review

Author:

Majumdar B,Rao K Ramoji,Rakshit S,Kal S,Lahiri S K

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

http://www.tandfonline.com/doi/pdf/10.1080/02564602.1990.11438669

Reference37 articles.

1. E E Hollis,Design of VLSI Gate Array ICs, Prentice Hall, New Jersey, 1987, pp 1–117 and 429–439.

2. A study on bipolar VLSI gate-arrays assuming four layers of metal

3. A versatile function generator chip implemented in an I/sup 2/L gate array

4. A 5K-gate bipolar masterslice LSI with a 500 ps loaded gate delay

5. A bipolar 230 ps masterslice cell array with 2600 gates

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Microelectronics Technology Development at IIT Kharagpur;IETE Technical Review;1990-09

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