A study on bipolar VLSI gate-arrays assuming four layers of metal-Reference-Cited by-同舟云学术

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A study on bipolar VLSI gate-arrays assuming four layers of metal

Published:1982-06 Issue:3 Volume:17 Page:472-480
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Klein K.,Miersch E.F.,Remshardt R.,Schettler H.,Schulz U.,Zuhlke R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22583/01051762.pdf?arnumber=1051762

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Package Wiring and Terminals;Microelectronics Packaging Handbook;1997

2. An Overview of Bipolar Gate Arrays and a Report of an IIL Gate Array Design and Development;IETE Technical Review;1990-09

3. Package Wiring and Terminals;Microelectronics Packaging Handbook;1989

4. Halbleiter- und Verbindungstechnologien (Packaging) in der IBM Deutschland;Datentechnik im Wandel;1986

5. Wirability-designing wiring space for chips and chip packages;IEEE Design & Test of Computers;1984-08

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