1. C. Bouras, J. Garofalakis, P. Spirakis, and V. Triantafillou, Queuing delays in differed multistage interconnection networks, in Proceedings of the 1987 ACM Simetrics Conference, May 11–14, Banff, AB, 1987, pp. 111–121
2. C. Bouras, J. Garofalakis, P. Spirakis, and V. Triantafillou, A general performance model for multistage interconnection networks, Euro-Par'97, August 25–29
3. An analytical performance model for multistage interconnection networks with finite, infinite and zero length buffers
4. Cheemalavagu, S. and Malek, M. 1982. “Analysis and simulation of banyan interconnection networks with 2 × 2, 4 × 4 and 8 × 8 switching elements”. 83–99. Los Angeles, CA: IEEE Computer Society Press. Proceedings Real-Time Systems Symposium, IEEE Computer Society
5. C.K. Chen, M. Atiquzzaman, D. Dowd, and E. Gelenbe, An improved model for performance analysis of multistage switches, in Proceedings of the Third International Workshops on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, IEEE Computer Society, IEEE Computer Society Press, Durham, NC, 1995, pp. 105–109