A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime
Author:
Affiliation:
1. School Of Electronics & Communication Engineering, Shri Mata Vaishno Devi University,Katra-(India)
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/1448837X.2021.1966957
Reference70 articles.
1. Leakage current reduction in CMOS VLSI circuits by input vector control
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4. Design and optimization of multithreshold cmos (mtcmos) circuits
5. Designing digital circuits with nano-scale devices: Challenges and opportunities
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