Fast multiplier design using redundant signed-digit numbers-Reference-Cited by-同舟云学术

Fast multiplier design using redundant signed-digit numbers

Published:1990-09 Issue:3 Volume:69 Page:359-368
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

RAJASHEKHARA T. N.,KAL O.

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

http://www.tandfonline.com/doi/pdf/10.1080/00207219008920321

Reference18 articles.

1. AGRAWAL , D. P. , et al. 1983 , On design and performance of VLSI based parallel multiplier .Proceedings of the 6th Symposium on Computer Arithmetic, pp. 17 – 21

2. Signed-Digit Numbe Representations for Fast Parallel Arithmetic

3. BOROVAC , R. T. , 1967 , The logical design of a class of limited carry-borrow propagation adders . Report 275 , Department of Computer Science, University of Illinois , Urbana , U.S.A

4. The Area-Time Complexity of Binary Multiplication

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