Hardmask engineering by mask encapsulation for enabling next generation reactive ion etch scaling
Author:
Affiliation:
1. Silicon Technology and Manufacturing 1 , Western Digital, Milpitas, California 95035
2. Non-Volatile Memory Research 2 , Western Digital, San Jose, California 95119
Abstract
Publisher
American Vacuum Society
Subject
Materials Chemistry,Electrical and Electronic Engineering,Surfaces, Coatings and Films,Process Chemistry and Technology,Instrumentation,Electronic, Optical and Magnetic Materials
Link
https://pubs.aip.org/avs/jvb/article-pdf/doi/10.1116/6.0002709/17984943/043202_1_6.0002709.pdf
Reference23 articles.
1. Challenges in high-aspect ratio contact (HARC) etching for DRAM capacitor formation
2. ChemInform Abstract: An Overview of Dry Etching Damage and Contamination Effects
3. Dry etching technology for 1-µm VLSI fabrication
4. Area selective deposition of ruthenium on 3D structures
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2. Understanding 3D anisotropic reactive ion etching of oxide-metal stacks;Journal of Vacuum Science & Technology B;2023-11-15
3. Extending area selective deposition of ruthenium onto 3D SiO2-Si multilayer stacks;Journal of Vacuum Science & Technology A;2023-08-25
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