Tilted ion implantation as a cost-efficient sublithographic patterning technique-Reference-Cited by-同舟云学术

Tilted ion implantation as a cost-efficient sublithographic patterning technique

Published:2016-07 Issue:4 Volume:34 Page:040608
ISSN:2166-2746
Container-title:Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
language:en
Short-container-title:Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena

Author:

Kim Sang Wan¹,Zheng Peng¹,Kato Kimihiko¹,Rubin Leonard²,King Liu Tsu-Jae³

Affiliation:

1. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720-1770

2. Axcelis Technologies, 108 Cherry Hill Drive, Beverly, Massachusetts 01915

3. Department of Electrical Engineering and Computer Sciences and Kavli Energy NanoSciences Institute, University of California, Berkeley, California 94720-1770

Funder

National Science Foundation (NSF)

Publisher

American Vacuum Society

Subject

Materials Chemistry,Electrical and Electronic Engineering,Surfaces, Coatings and Films,Process Chemistry and Technology,Instrumentation,Electronic, Optical and Magnetic Materials

Link

http://scitation.aip.org/deliver/fulltext/avs/journal/jvstb/34/4/1.4953085.pdf?itemId=/content/avs/journal/jvstb/34/4/10.1116/1.4953085&mimeType=pdf&containerItemId=content/avs/journal/jvstb

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1. Demonstration of a novel tunnel FET with channel sandwiched by drain;Semiconductor Science and Technology;2019-11-29

2. Tilted ion implantation of spin-coated SiARC films for sub-lithographic and two-dimensional patterning;Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019;2019-03-26

3. Extending the era of Moore's Law;Photomask Technology;2017-10-16

4. Sub-lithographic Patterning via Tilted Ion Implantation for Scaling Beyond the 7-nm Technology Node;IEEE Transactions on Electron Devices;2017-01

5. Embedded Nano-Electro-Mechanical Memory for Energy-Efficient Reconfigurable Logic;IEEE Electron Device Letters;2016-12