Isadora: automated information-flow property generation for hardware security verification-Reference-Cited by-同舟云学术

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Isadora: automated information-flow property generation for hardware security verification

Published:2022-11-11 Issue: Volume: Page:
ISSN:2190-8508
Container-title:Journal of Cryptographic Engineering
language:en
Short-container-title:J Cryptogr Eng

Author:

Deutschbein Calvin^ORCID,Meza Andres,Restuccia Francesco,Kastner Ryan,Sturton Cynthia

Funder

NSF

Intel

Semiconductor Research Corporation

Publisher

Springer Science and Business Media LLC

Subject

Computer Networks and Communications,Software

Link

https://link.springer.com/content/pdf/10.1007/s13389-022-00306-w.pdf

Reference43 articles.

1. Ammons, G., Bodík, R., and Larus, J.R.: Mining specifications. In 29th Symposium on Principles of Programming Languages (POPL). ACM, 4–16. (2002) https://doi.org/10.1145/503272.503275

2. Ardeshiricham, A., Hu, W., Marxen, J., Kastner, R.: Register transfer level information flow tracking for provably secure hardware design. In Design. Automation Test in Europe Conference Exhibition (DATE) 2017, 1691–1696 (2017)

3. Bilzor, M., Huffmire, T., Irvine, C., Levin, T.: Security checkers: Detecting processor malicious inclusions at runtime. In International Symposium on Hardware-Oriented Security and Trust (HOST). IEEE, 34–39 (2011)

4. Brown, M.: Cross-validation processor specifications. Master’s thesis, University of North Carolina at Chapel Hill (2017)

5. Chang, P.-H., Wang, L.C.: Automatic assertion extraction via sequential data mining of simulation traces. In 15th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 607–612 (2010)

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs;Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy;2023-10-29

2. Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

3. Information Flow Verification;Handbook of Computer Architecture;2022

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