Isadora: automated information-flow property generation for hardware security verification
Author:
Funder
NSF
Intel
Semiconductor Research Corporation
Publisher
Springer Science and Business Media LLC
Subject
Computer Networks and Communications,Software
Link
https://link.springer.com/content/pdf/10.1007/s13389-022-00306-w.pdf
Reference43 articles.
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2. Ardeshiricham, A., Hu, W., Marxen, J., Kastner, R.: Register transfer level information flow tracking for provably secure hardware design. In Design. Automation Test in Europe Conference Exhibition (DATE) 2017, 1691–1696 (2017)
3. Bilzor, M., Huffmire, T., Irvine, C., Levin, T.: Security checkers: Detecting processor malicious inclusions at runtime. In International Symposium on Hardware-Oriented Security and Trust (HOST). IEEE, 34–39 (2011)
4. Brown, M.: Cross-validation processor specifications. Master’s thesis, University of North Carolina at Chapel Hill (2017)
5. Chang, P.-H., Wang, L.C.: Automatic assertion extraction via sequential data mining of simulation traces. In 15th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 607–612 (2010)
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2. Information Flow Verification;Handbook of Computer Architecture;2022
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