1. G.G. Kumar, S.K. Sahoo, Implementation of a high speed multiplier for high performance and low power applications, in Proceedings of the IEEE 19th International Symposium on VLSI Design and Test (VDAT) (2015), pp. 1–4
2. V. Sharma, A. Kumar, Design, implementation & performance of vedic multiplier for different bit lengths. Int. J. Innovative Res. Comput. Commun. Eng. 5(4), 7912–7919 (2017). ISSN: 2320-9801(O), 2320-9798(P)
3. A. Kumar, V. Sharma, Comparative analysis of vedic & array multiplier. Int. J. Electron. Commun. Eng. Technol. 8(3), 17–27 (2017). ISSN: 0976-6464 (P), 0976-6472
4. A. Kumar, E. Gupta, R.A. Shobhit, R.K. Jain, Comparative research for managing delay in signal processing via multipliers, in Proceedings of 2nd IEEE International Conference on Power Electronics, Intelligent control and energy Systems (ICPIECES-2018), DTU, India (2018), pp. 1549–1554. ISBN: 978-1-5386-6626-5
5. A. Kumar, R.P. Agarwal, An approach to manage delay in signal processing via selected multiplier algorithms, in Proceedings of 3rd IEEE International Conference on Inventive Computation Technologies (3rd ICICT 2018) Conference Proceedings, RVS Technical Campus, Coimbatore, Tamil Nadu, India (2018), pp. 401–405. ISBN: 978-1-5386-4985-5