1. Takeda, K., et al.: A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications. IEEE J. Solid-State Circuits 41(1) (2006)
2. Thakare, P.V., Tembhurne, S.: A power analysis of SRAM cell using 12T topology for faster data transmission. Int. J. Sci. Technol. Eng. 2, 441–446 (2016)
3. Singh, W., Kumar, A.G.: Design of 6T, 5T and 4T SRAM cell on various performance metrics. In: 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 899–904 (2015)
4. Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd ed. Prentice-Hall, Englewood Cliffs, NJ (2003)
5. Kiran, P.N.V., Saxena, N.: Design and analysis of different types SRAM cell topologies. In: IEEE Sponsored 2nd International Conference on Electronics and Communication System (ICECS 2015), pp. 167–173 (2015)