Pseudo-BIST: A Novel Technique for SAR-ADC Testing-Reference-Cited by-同舟云学术

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Pseudo-BIST: A Novel Technique for SAR-ADC Testing

Published:2017 Issue: Volume: Page:168-178
ISSN:1865-0929
Container-title:Communications in Computer and Information Science
language:
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Author:

Gupta Yatharth,Deb Sujay,Singh Vikrant,Srinivasan V. N.,Sharma Manish,Das Sabyasachi

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-7470-7_18

Reference8 articles.

1. John, D., Martin, K.: Analog Integrated Circuits. Wiley, New York (1997)

2. Poehl, F., et al.: Production test challenges for highly integrated mobile phone SoCs. In: Proceedings of IEEE European Test Symposium, pp. 17–22 (2010)

3. Blair, J.: Histogram measurement of ADC nonlinearities using sine waves. IEEE Trans. Instr. Meas 43(3), 373–383 (1994)

4. Zagursky, V., Gertners, A.: Testing technique for embedded ADC. In: IEEE Asia-Pacific Conference on Circuits and Systems, Microelectronics and Integrating Systems, APCCAS 1998, Proceedings (Cat. No. 98EX242), Chiangmai, pp. 775–778 (1998)

5. Goyal, S., et al.: Test time reduction of successive approximation register A/D converter by selective code measurement. In: IEEE International Conference on Test, Austin, TX, pp. 8, 225 (2005)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An On Chip BIST Architecture for ADC Parameter Testing and Measurement;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

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