Author:
Borkute D. P.,Dakhole P. K.,Nawre Nayan Kumar
Reference9 articles.
1. Vasundara Patel, Gurumurthy\Applications in Multi Valued Logic” International Journal of VLSI Design & Communication Systems(IJVCS)Vol1, No.1, March 2010.
2. Kostas Pagiamtzis, Ali Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 3, MARCH 2006.
3. R.C.G daSilva, C. Lazzari, H. Boudinovc, L. Carro, “CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs” Microelectronics Journal 40(2009) 14661470, 2007.
4. Deepti P. Borkute, Dr. Dakhole P.K. “Impact of Quaternary Logic on Performance of Look-Up Table” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 3, Ver. II (May–Jun. 2015), pp. 36–48 e-ISSN: 2319-4200.
5. Diogo Brito, Taimur G. Rabuske, Jorge R. Fernandes, Paulo Flores and Jos Monteiro, \Quaternary Logic Lookup Table in Standard CMOS “ IEEE Transactions On Very Large Scale Integration (Vlsi) Systems 1063–8210 2014 IEEE.