Design High-Frequency and Low-Power 2-D DWT Based on 9/7 and 5/3 Coefficient Using Complex Multiplier
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Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-33-4305-4_32
Reference14 articles.
1. Gardezi SEI, Aziz F, Javed S, Younis CJ, Alam M, Massoud Y (2019) Design and VLSI implementation of CSD based DA architecture for 5/3 DWT. 978-1-5386-7729-2/19/$31.00©2019 IEEE
2. Mohamed Asan Basiri M, Noor Mahammad S (2018) An efficient VLSI architecture for convolution based DWT Using MAC. In: 31th international conference on VLSI design and 2018, 17th international conference on embedded systems. IEEE
3. Chakraborty A, Chakraborty D, Banerjee A (2017) A memory efficient, high throughput and fastest 1D/3D VLSI architecture for reconfigurable 9/7 & 5/3 DWT filters. In: International conference on current trends in computer, electrical, electronics and communication (ICCTCEEC-2017)
4. Biswas R, Malreddy SR, Banerjee S (2017) A high precision-low area unified architecture for lossy and lossless 3D multi-level discrete wavelet transform. Trans Circuits Syst Video Technol 45(5)
5. Bhairannawar SS, Kumar R (2016) FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme. In: 2016 International conference on vlsi systems, architectures, technology and applications (VLSI-SATA)
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