Author:
Aggarwal Arushi,Pandey Bishwajeet,Dabbas Sweety,Agarwal Achal,Saurabh Siddharth
Reference9 articles.
1. Kumar, R., et al.: A novel and high performance implementation of 8 × 8 multiplier based on Vedic mathematics using 90 nm Hybrid PTL/CMOS logic. Int. J. Comput. Appl. 69(27)
2. Thapliyal, H., Arabnia, H.R.: A Time-area-power efficient multiplier and square architecture based on ancient Vedic mathematics. Department of Computer Science, The University of Georgia, Georgia 30602-7404, U.S.A
3. Kumar, P., Radhika, A.: FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter. In: International Conference on Energy Efficient Technologies for Sustainability (ICEETS) IEEE, Nagercoil, pp. 14–17 (2013)
4. Innocent, R., et al.: High speed Vedic multiplier for digital signal processors. IETE J. Res. 55(6) (2009)
5. Saligram, R., et al.: Optimized reversible Vedic multipliers for high speed low power operations. In: Proceedings of IEEE Conference on Information and Communication Technologies (ICT), JeJu Island, pp. 809–814 (2013)
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