Automated Deadlock Verification for On-Chip Cache Coherence and Interconnects Through Extended Channel Dependency Graph
Publisher
Springer Singapore
Reference11 articles.
1. Bi, J., Yuan, H., Tan, W.: Deadlock prevention for service orchestration via controlled Petri nets. J. Parallel Distrib. Comput. 124, 92–105 (2018).
https://doi.org/10.1016/j.jpdc.2018.09.010
2. Chatterjee, S., Kishinevsky, M.: Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics. In: Touili, T., Cook, B., Jackson, P. (eds.) Computer Aided Verification, pp. 321–338. Springer, Berlin (2010)
3. Fraigniaud, P., Fleury, E.: A general theory for deadlock avoidance in wormhole-routed networks. IEEE Trans. Parallel Distrib. Syst. 9, 626–638 (1998).
https://doi.org/10.1109/71.707539
4. German, S.M.: Formal design of cache memory protocols in IBM. Formal Meth. Syst. Des. 22(2), 133–141 (2003).
https://doi.org/10.1023/A:1022921522163
5. Lecture Notes in Computer Science;A Gotmanov,2011