Effect of Various Structure Parameters on Electrical Characteristics of Double Gate FinFET
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-0700-3_26
Reference11 articles.
1. Roy K, Mukhopadhyay S, Mahmoodi H (2003) Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits. Proc IEEE 91(2):305–327. IEEE
2. Khanna VK (2016) Integrated nanoelectronics: nanoscale CMOS. Springer, Post-CMOS and Allied Nanotechnologies
3. Jung Analytical models of threshold voltage and drain-induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide. AIMS Electron Electr Eng 6(2):108–123
4. Panchanan S, Maity R, Baishya S, Maity NP (2022) Modelling, simulation and performance analysis of drain current for Below 10 nm channel length based Tri-gate FinFET. SILICON 14:11519–11530
5. Boukortt NEI, Lenka TR, Patane S, Crupi G (2022) Effects of varying the fin width, fin height, gate dielectric material, and gate length on the DC and RF performance of a 14-nm SOI FinFET structure. Electronics11(1):91
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