Design and DC Electrical Performance Analysis of SOI-Based SiO2/HfO2 Dual Dielectric Gate-All-Around Vertically Stacked Nanosheet at 5 nm Node
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-0973-5_58
Reference24 articles.
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2. Mohapatra E, Dash TP, Jena J, Das S, Maiti CK (2021) Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Appl Sci 3(5):1–13
3. Lee Y, Park GH, Choi B, Yoon J, Kim HJ, Kim DH, Choi SJ (2020) Design study of the gate-all-around silicon nanosheet MOSFETs. In: Semiconductor science and technology, IOP, pp 1–6
4. Ryu D, Kim M, Yu J, Kim S, Lee J-H, Park B-G (2020) Investigation of sidewall high-k interfacial layer effect in gate-all-around structure. IEEE Trans Electron Devices 67(4):1859–1863
5. Vashishtha V, Clark LT (2021) Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. Microelectron J 107:104942
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