An Improved Pseudo-Domino Technique for Low-Power Applications
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-0312-0_45
Reference15 articles.
1. Dadoria AK, Khare K, Gupta TK, Singh RP (2017) Ultra low power FinFET based domino circuits. Int J Electron. https://doi.org/10.1080/00207217.2017.1279227
2. Pandey AK, Verma PK, Verma R (2018) Analysis of noise immunity for wide OR footless domino circuit using keeper controlling network. Circuits Syst Sig Process. https://doi.org/10.1007/s00034-018-0781-0
3. Garg S, Gupta TK (2020) A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET. Circuit World. https://doi.org/10.1108/CW-09-2019-0128
4. Asyaei M (2015) A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology. Integr VLSI J. https://doi.org/10.1016/j.vlsi.2015.06.003
5. Singhal S, Mehra A, Tripathi U (2019) Power reduction in domino logic using clock gating in 16 nm CMOS technology. Sig Process Integr Netw. https://doi.org/10.1109/SPIN.2019.8711713
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