A High Speed Two Step Flash ADC-Reference-Cited by-同舟云学术

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A High Speed Two Step Flash ADC

Published:2018 Issue: Volume: Page:826-836
ISSN:1865-0929
Container-title:Soft Computing Systems
language:
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Author:

Krishna K. Lokesh^ORCID,Al-Naamani Yahya Mohammed Ali,Anuradha K.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-13-1936-5_84

Reference9 articles.

1. Nasri, B., Sebastian, S.P., You,K.D., RanjithKumar, R., Shahrjerdi, D.: A 700 μW 1GS/s 4-bit folding-flash ADC in 65 nm CMOS for wideband wireless communications. In: 2017 International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, pp. 1–4. IEEE (2017)

2. Wang, G., Lu, W., Zhang, L., Zhang, Y., Chen, Z.: 14-bit 20 μW column level two step ADC for 640 × 512 IRFPA. Electron. Lett. 51(14), 1054–1056 (2013)

3. Varzaghani, A., et al.: 10.3GS/s, 6-Bit Flash ADC for 10G ethernet applications. IEEE J. Solid-State Circ. 48(12), 3038–3048 (2013)

4. Ferragina, V., Ghittori, N., Maloberti, F.: Low-power 6-bit flash ADC for high-speed data converters architectures. In: 2006 International Symposium on Circuits and Systems, Island of Kos. IEEE (2006)

5. Ritter, P., Le Tual, S., Allard, B., Möller, M.: Design considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC without track-and-hold. IEEE J. Solid-State Circ. 49(9), 1886–1894 (2014)

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1. Implementation of a CMOS Operational Amplifier using Composite Cascode Stages;2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS);2019-03

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