Junctionless Gaussian Doped Negative Capacitance SOI Transistor: Investigation of Device Performance for Analog and Digital Applications
Author:
Mehta HemaORCID,
Kaur HarsupreetORCID
Publisher
Springer Singapore
Reference24 articles.
1. Borkar S (1999) Design challenges of technology scaling. IEEE Micro 19(4):23–29
2. Cavin RK, Zhirnov VV, Hutchby JA, Bourianoff GI (2005) Energy barriers, demons and minimum energy operation of electronic devices. Fluctuations Noise Lett 5(4):C29–C38
3. Kuhn KJ (2012) Considerations for ultimate CMOS scaling. IEEE Trans Electron Devices 59(7):1813–1828
4. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-S (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89:259–288
5. Colinge J-P, Lee C-W, Afzalian A, Dehdashti Akhavan N, Yan R, Ferain I, Razavi P, O’Neill, Blake A, White M, Kelleher A-M, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229