3D Circuit Model Construction and Simulation

Author:

Tan Cher Ming,He Feifei

Publisher

Springer Singapore

Reference50 articles.

1. Complete timing signoff in the nanometer era, http://w2.cadence.com/whitepapers/timing_signoff_wp.pdf

2. Baker RJ (2004) CMOS circuit design—layout and simulation, revised 2nd edn. IEEE Press Series on microelectronic Systems, Wiley, London

3. Tan CM, He F (2009) 3D circuit model for 3D IC reliability study. In: 10th International conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems (EuroSimE), 2009, p 7

4. Tan CM, Hou Y, Li W (2007) Revisit to the finite element modeling of electromigration for narrow interconnects. J Appl Phys 102(2):033705-1-7

5. He F, Tan CM (2010) Circuit level interconnect reliability study using 3D circuit model. Microelectron Reliab 50(3):376–390

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