Trimmed-TDL-Based Time-to-Digital Converter for Time-of-Flight Applications Implemented on Cyclone V FPGA
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-1916-1_17
Reference24 articles.
1. Cao G, Xia H, Dong N (2018) An 18-ps tdc using timing adjustment and bin realignment methods in a cyclone-iv fpga. Rev Sci Instrum 89(5):054707
2. El-Hadbi A, Elissati O, Fesquet L (2019) Time-to-digital converters: a literature review and new perspectives. In: 2019 5th international conference on event-based control, communication, and signal processing (EBCCSP). IEEE, pp 1–8
3. Garzetti F, Corna N, Lusardi N, Geraci A (2021) Time-to-digital converter ip-core for fpga at state of the art. IEEE Access 9:85515–85528
4. Jiao Y, Zhang Q, Chen W, Zhou L, Chen C (2021) A resource-saving dual channel time-to-digital converter with shared tapped delay line in fpgas. J Instrum 16(01):P01012
5. Kwiatkowski P, Szplet R (2020) Multisampling wave union time-to-digital converter. In: 2020 6th international conference on event-based control, communication, and signal processing (EBCCSP). IEEE, pp 1–5
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