Accomplishing Low-Power Consumption with TFET
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_31
Reference25 articles.
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2. Saravanan M, Parthasarathy E. A review of III-V tunnel field effect transistors for future ultra low power digital/analog applications. Microelectron J. 2021;114:105102.
3. Pravin ND, Prajoon P, Ajayan J. Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications. Phys E Low-dimensional Syst Nanostruct. 2016;83:95.
4. Darshana V, Balamurugan NB, Arun Samuel TS. An analytical modeling and simulation of surrounding gate TFET with an impact of dual material gate and stacked oxide for low power applications. J Nano Res. 2019;57:68.
5. Sathish Kumar M, Samuel TA, Ramkumar K, Anand IV, Rahi SB. Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET. Superlattice Microst. 2022;162:107099.
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