3D Stacked IC Chip Design: From CMOS to 2D Materials
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_57
Reference12 articles.
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2. Wang C-C, Sung G-N. A low-power 2D bypassing multiplier using 0.35 μm CMOS technology. In: IEEE computer society annual symposium on emerging VLSI technologies and architectures (ISVLSI'06). Karlsruhe; 2006. p. 4. https://doi.org/10.1109/ISVLSI.2006.5.
3. Banjevic M, Furrer B, Popovic RS. 2D CMOS integrated magnetometer based on the miniaturized circular vertical hall device. In: TRANSDUCERS 2009 – 2009 international solid-state sensors, actuators and microsystems conference. Denver; 2009. p. 877–80. https://doi.org/10.1109/SENSOR.2009.5285857.
4. Choi B-S, et al. CMOS image sensor using pixel aperture technique for single-chip 2D and 3D imaging. In: 2017 IEEE sensors. Glasgow; 2017. p. 1–3. https://doi.org/10.1109/ICSENS.2017.8234113.
5. Hinton H, et al. A 200 × 256 image sensor heterogeneously integrating a 2D nanomaterial-based photo-FET Array and CMOS time-to-digital converters. In: 2022 IEEE international solid- state circuits conference (ISSCC). San Francisco; 2022. p. 1–3. https://doi.org/10.1109/ISSCC42614.2022.9731685.
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