Author:
Asha K. S.,Mendonca Oswald Sunil,Bhandarkar Rekha,Srinivas R.
Reference10 articles.
1. Potkonjak M, Qu G, Koushanfar F, Chang CH (2017) 20 Years of research on intellectual property protection. In: 2017 IEEE international symposium on circuits and systems (ISCAS). IEEE, pp 1–4
2. Rajendran J, Dhandayuthapany AM, Vedula V, Karri R (2016) Formal security verification of third party intellectual property cores for information leakage. In: 2016 29th international conference on VLSI design and 2016 15th international conference on embedded systems (VLSID). IEEE, pp 547–552
3. Sen L, Roy A, Bhattacharjee S, Mittra B, Roy SK (2010) DFT logic verification through property based formal methods: SOC to IP. In: Proceedings of the 2010 conference on formal methods in computer-aided design. FMCAD Inc., pp 33–34
4. Liao WS, Hsiung PA (2003) FVP: a formal verification platform for SoC. In: Proceedings of IEEE international SOC conference (systems-on-chip), 2003. IEEE, pp 21–24
5. Stoffel D (2009) Formal verification of systems-on-chip-industrial experiences and scientific perspectives. In: 2009 20th international workshop on database and expert systems application. IEEE, pp 3-3