Publisher
Springer Nature Singapore
Reference10 articles.
1. Dhanumjaya SK, Sudha M, Giri Prasad MN, Padmaraju K (2012) Cell stability analysis of conventional 6T dynamic and 8T SRAM cell in 45nm technology. Int J VLSI Design Commun Syst 3(2)
2. Trivedi VP, Fossum JG (2004) Source/drain-doping engineering, for optimal nanoscale FinFET design. In: International SOI conference, pp 192–194
3. Alluri S (2019) High performance SR latch in VLSI circuits using FINFET 18nm technology. J Continua Math Sci ISSN 14(6):329–346
4. Nanda S, Dhar RS Implementation and characterization of 14 nm trigate HOI n-FinFET using strained silicon channel with reduced area on chip. In: 6th international conference for convergence in technology (I2CT), pp. 1–4. IEEE, India (2021)
5. Gupta V, Khandelwal S (2015) Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories. In: Nirma University international conference on engineering (NUiCONE), 978-1-4799-9991-0/15/©2015 IEEE