Author:
Ghoshal Pranati,Sen Sunit Kumar
Reference12 articles.
1. Kharate, G.K.: Digital Electronics. Oxford University Press (2012)
2. Daegyu, L., Cheol, Y.J., Kyusun, C., Ghaznavi, J.: Fat tree encoder design for ultra-high speed flash A/D converters, circuits and systems. In: the 45th Midwest Symposium, pp. 87–90 (2002)
3. Agarwal, N., Paily, R.: An improved ROM architecture for bubble error suppression in high speed flash ADCs. In: Proceedings of AISPC, pp. 1–5 (2008)
4. Uyttenhove, K., Marques, A., Steyaert, M.: A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction. In: Proceedings of the IEEE Conference, pp. 249–252 (2000)
5. Mangelsdorf, C.: A 400-MHz input flash converter with error correction. IEEE J. Solid-State Circuits 25(1), 184–191 (1990)
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