Author:
Yuan Hengzhou,Chen Jianjun,Liang Bin,Guo Yang
Reference9 articles.
1. Wadekar, J., et al.: A 0.5–4 GHz programmable-bandwidth fractional-N PLL for multi-protocol SERDES in 28 nm CMOS. In: 2016 29th International Conference on VLSI Design, vol. 41, pp. 236–239 (2016)
2. Kauppila, A.V., et al.: Analysis of the single event effects for a 90 nm CMOS phase-locked loop. In: Proceedings of the Radiation Effects Components and Systems (RADECS), pp. 201–206, September 2009
3. Loveless, T.D., et al.: A hardened-by-design technique for RF digital phase-locked loops. IEEE Trans. Nucl. Sci. 53(6), 3432–3438 (2006)
4. Loveless, T.D., et al.: A single-event-hardened phase-locked loop fabricated in 130 nm CMOS. IEEE Trans. Nucl. Sci. 54(6), 2012–2020 (2007)
5. She, X., et al.: Single event transient tolerant frequency divider. IET Comput. Digit. Tech. 8(3), 140–147 (2014)