Low Power, Noise-Immune High Performance Arithmetic Adder Circuit Design Using Modified Parallel Prefix Adders
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-4960-9_58
Reference22 articles.
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3. Kulkarni RR (2015) Comparison among different adders. IOSR J VLSI Signal Process (IOSR-JVSP) 5(6):01–06
4. Sher T-H, Arab S (2015) Comparisons between ripple-carry adder and carry-look-ahead adder. Technical report, University of Southern California
5. Sai CL et al (2021) 5:3 compressor based neural network with LM algorithm in multiplier as application. IOP Conf Ser Mater Sci Eng 1042:012033
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