Analysis of Low-Power Cache Memory Design for Single Bit Architecture
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-7909-4_15
Reference25 articles.
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2. Fragasse, R., et al.: Analysis of SRAM enhancements through sense amplifier capacitive offset correction and replica self-timing. IEEE Trans. Circ. Syst. I Regul. Pap. 66(6), 2037–2050 (2019)
3. Gupta, S., Gupta, K., Calhoun, B.H., Pandey, N.: Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS. IEEE Trans. Circ. Syst. I Regul. Pap. 66(3), 978–988 (2019)
4. Dounavi, H., Sfikas, Y., Tsiatouhas, Y.: Periodic aging monitoring in SRAM sense amplifiers. In: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), Platja d'Aro, pp. 12–16 (2018)
5. Ahmad, S., Iqbal, B., Alam, N., Hasan, M.: Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis. IEEE Trans. Dev. Mater. Reliab. 18(3), 337–349 (2018)
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