Design of Low Power Area Efficient 7:3 Counter
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-7985-8_116
Reference13 articles.
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3. Navin KM et al (2019) Symmetric stacking binary counter. Int J Commun Comput Technol 7:11–18. https://doi.org/10.31838/ijccts/07. SP01 3
4. Santhi C, Babu MG (2018) Symmetric stacked fast binary counters based on reversible logic. Int J Eng Technol 7(4):2747–2752
5. Asif S, Kong Y (2015). Design of an algorithmic Wallace multiplier using high speed counters. In: 2015 Tenth international conference on computer engineering & systems (ICCES), pp 133–138. IEEE, December
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