Design and Technology Co-optimization for Investigating Power, Performance, Area and Cost Trade-Offs in FinFET Technologies

Author:

Kumbar Vijayalaxmi,Raut Vaishali

Publisher

Springer Nature Singapore

Reference18 articles.

1. Thompson SE, Parthasarathy S (2006) Moore’s law: the future of Si microelectronics. Mater Today 9(6):20–25

2. Colinge JP (ed.) FinFETs and other multi-gate transistors, vol 73. Springer, New York

3. Beintner J, Bronner GB, Divakaruni R, Li Y (2008) U.S. patent no. 7,470,570. U.S. Patent and Trademark Office, Washington, DC

4. Bhattacharya D, Jha NK (2014) FinFETs: from devices to architectures. Adv Electron

5. Liaw JJ (2015) U.S. patent no. 9,041,115. U.S. Patent and Trademark Office, Washington, DC

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2. A Comparative Analysis of FinFET Based SRAM Design;International Journal of Electrical and Electronics Research;2022-12-30

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