A 12-bit Low-power 50MS/s SAR ADC Optimized for Speed and Power in 45 nm CMOS Technology-Reference-Cited by-同舟云学术

A 12-bit Low-power 50MS/s SAR ADC Optimized for Speed and Power in 45 nm CMOS Technology

Published:2022-08-30 Issue: Volume: Page:71-86
ISSN:1876-1100
Container-title:Advances in Communication, Devices and Networking
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Author:

Akshatha M. S.,Nagabushanam M.

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-19-2004-2_7

Reference14 articles.

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2. Delgado-Restituto M, Carrasco-Robles M, Fiorelli R, Gines-Arteaga AJ, Rodriguez-Vzquez A (2016) A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications. In IEEE Asia Pacific conference on circuits and systems (APCCAS), pp421–424

3. Suneel Krishna RVNR, Shankar A (2013) Design of low power SAR-ADC in 0.18μm mixed-mode CMOS process. Int J Res Comput Commun Technol 2(8): 654–658.

4. Singh VP, Sharma GK, Shukla A (2017) 8-Bit high speed, power efficient SAR ADC designed in 90 nm CMOS technology. IN: International conference on computing, communication and networking technologies (ICCCNT), pp 1–5

5. Bobade N, Mahendra, Gaikwad A, Dhande JD (2014) Design of successive approximation analog to digital converter with modified DAC. Int J Eng Res Technol (IJERT) 3(7)

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1. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15