Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory
Author:
Tak Sheetal,Mali Madan
Publisher
Springer Singapore
Reference18 articles.
1. Chen Q, Mahmoodi H, Bhunia S, Roy K (2005) Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans Very Large Scale Integr Syst 13(11):1286–1295. https://doi.org/10.1109/TVLSI.2005.859565
2. Ney A, Dilillo L, Girard P et al (2009) A new design-for-test technique for SRAM core-cell stability faults. In: Proceedings of design automation and test conference, Nice, France, 20–24 April 2009
3. Irobi S, Al-Ars Z, Hamdioui S (2010) Detecting memory faults in the presence of bit line coupling in SRAM devices. Proc Int Test Conf. https://doi.org/10.1109/TEST.2010.5699246
4. Mali M, Sutaone M, Tak S (2009) Gating transistor power saving technique for power optimized code book SRAM. In: Proceedings of international conference on advanced computing and communications control (ICAC3’09), pp 581–584. https://doi.org/10.1145/1523103.1523220
5. Mali M, Sutaone M, Tak S (2009) 5Gbits/s, 300 mV precharge, 256b, low power rhythmic SRAM. In: (ARTCom 2009) International Conference on Advances in Recent Technologies in Communication and Computing, pp 554–558. https://doi.org/10.1109/ARTCom.2009.223