Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-15-8221-9_199
Reference15 articles.
1. Awasthi V, Raj K (2014) Design of efficient digital filter using cutset retiming technique. Int J Electron Electr Comput Syst IJEECS 2(1). ISSN 2348-117X
2. Meher PK (2016) On efficient retiming of fixed-point circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(4):1257–1265
3. Meher PK (2015) Seamless pipelining of DSP circuits. J Circ Syst Signal Process [Online]. Available: https://link.springer.com/article/10.1007%2Fs00034-015-0089-2
4. Mehra H, Bhat MS (2018) High level optimization methodology for high performance DSP systems using retiming techniques. In: 2018 IEEE Distributed computing, VLSI, electrical circuits and robotics (DISCOVER)
5. Ryu S, Park N, Kim J-J (2019) Feed forward cutset free pipelined multiply—accumulate unit for machine learning accelerator. IEEE Trans Very Large Scale Integr (VLSI) Syst 27(1)
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