Novel Approach for the Reduction of Critical Paths in Static Timing Analysis Without Degradation in QOR
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-0055-8_17
Reference4 articles.
1. Fuchs K, Pabst M, Rossel T (1994) RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. IEEE Trans Comput Aided Des Integr Circuits Syst 13(12):1550–1562
2. Tragoudas S, Karayiannis D (1999) A fast nonenumerative automatic test pattern generator for path delay faults. IEEE Trans Comput Aided Des Integr Circuits Syst 18(7):1050–1057
3. Schulz MH, Fuchs K, Fink F (1989) Advanced automatic test pattern generation techniques for path delay faults. In: The nineteenth international symposium on fault-tolerant computing. Digest of papers, pp 44–51
4. Bhattacharya D, Agrawal P, Agrawal VD (1992) Delay fault test generation for scan/hold circuits using Boolean expressions. In: Proceedings 29th ACM/IEEE design automation conference, pp 159–164
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