Development of Low Power and Area Efficient Multi-core Memory Controller Using AXI4-Lite Interface Protocol

Author:

Chebiyyam Santhi,Gurunadha Babu M.,Ajay Kumar M.,Radhika Rani L.

Publisher

Springer Nature Singapore

Reference23 articles.

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2. Mück T, Fröhlich AA, Gracioli G, Rahmani A, Dutt N (2018) Chipsahoy: a predictable holistic cyber-physical hypervisor for mpsocs. In: International conference on embedded computer systems: architectures, modeling and simulation (SAMOS), Samos Island, Greece, pp 1–8

3. Saidi S, Syring A (2018) Exploiting locality for the performance analysis of shared memory systems in MPSoCs. In: 2018 IEEE real-time systems symposium (RTSS). IEEE, pp 350–360

4. Gracioli G, Alhammad A, Mancuso R, Fröhlich AA, Pellizzoni R (2015) A survey on cache management mechanisms for real-time embedded systems. ACM Comput Surv 48(2)

5. Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2013) Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: 2013 IEEE 19th Real-time and embedded technology and applications symposium (RTAS), pp 55–64

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